ASM1130 CROSS ASSEMBLER V1.22 -- V2M12 -- Sun Nov 1 19:25:09 2020 Source File: \u4bidec.asm TWO-WORD BINARY TO DECIMAL CONVERSION 2 | *************************************************** U4A00020 3 | * * U4A00030 4 | * SUBROUTINE NAME- * U4A00040 5 | * FULL NAME- BINARY TO DECIMAL TWO-WORD * U4A00050 6 | * INTEGER CONVERSION ROUTINE. * U4A00060 7 | * CODE NAME- BIDEC * U4A00070 8 | * PURPOSE- THIS SUBROUTINE CONVERTS A TWO- WORD * U4A00080 9 | * BINARY INTEGER TO A DECIMAL VALUE EXPRESSED* U4A00090 10 | * IN 11 WORDS CONTAINING 11 UNPACKED HOLL- * U4A00100 11 | * ERITH CHARS. * U4A00110 12 | * METHOD- * U4A00120 13 | * SEE IBM 1130 SUBROUTINE LIBRARY MANUAL * U4A00130 14 | * CAPABILITIES AND LIMITATIONS- * U4A00140 15 | * SEE IBM 1130 SUBROUTINE LIBRARY MANUAL * U4A00150 16 | * SPECIAL FEATURES- N/A * U4A00160 17 | * ADDITIONAL INFORMATION- * U4A00170 18 | * ESTIMATED EXECUTION TIME- * U4A00180 19 | * SEE IBM 1130 SUBROUTINE LIBRARY MANUAL * U4A00190 20 | * * U4A00200 21 | *************************************************** U4A00210 TWO-WORD BINARY TO DECIMAL CONVERSION 23 | LIBR U4A00230 24 | ENT BIDEC U4A00240 0000 6937 25 | BIDEC STX 1 SAV1+1 SAVE XR1 U4A00250 0001 6580 0000 26 | LDX I1 *-* RECORD ENTRY U4A00260 0003 D848 27 | STD SAVAQ SAVE BINARY DATA AND U4A00270 0004 2836 28 | STS SAVST STATUS U4A00280 29 | * U4A00290 0005 6903 30 | STX 1 *+3 SAVE PARAMETER ADDR U4A00300 0006 7101 31 | MDX 1 +1 INCRE FOR RET U4A00310 0007 6936 32 | STX 1 BD060+1 SET UP TO RET U4A00320 33 | * U4A00330 0008 6580 0000 34 | LDX I1 *-* OUT ADDR TO XR1 U4A00340 000A 71FF 35 | MDX 1 -1 U4A00350 000B 6923 36 | STX 1 BD040+1 SET UP OUTPUT ADDR U4A00360 000C 6A2D 37 | STX 2 SAV2+1 SAVE XR2 U4A00370 000D C83E 38 | LDD SAVAQ U4A00380 000E 4C10 003FR 39 | BSC L BD050,- BR ON POSITIVE U4A00390 40 | * U4A00400 0010 C034 41 | LD H4000 SET SIGN OF NEG AND SET U4A00410 0011 D035 42 | STO SIGN TO STORE INTO BUFFER U4A00420 43 | * U4A00430 44 | * U4A00440 0012 10A0 45 | SLT 32 U4A00450 0013 9838 46 | SD SAVAQ TAKE COMPLEMENT TO CHK FOR U4A00460 0014 4810 47 | BSC - LARGEST NEG NUMBER U4A00470 0015 D836 48 | STD SAVAQ U4A00480 0016 7006 49 | MDX BD010 GO TO HANDLE ON POSITIVE U4A00490 50 | * U4A00500 0017 180C 51 | SRA 12 IF NEG, SET TO RETURN U4A00510 0018 D500 000B 52 | STO L1 11 DECIMAL VALUE OF LARGEST U4A00520 001A 610A 53 | LDX 1 10 NEGATIVE NUMBER. U4A00530 001B C82E 54 | LDD DUMMY FETCH MOD U4A00540 001C 7002 55 | MDX BD010+2 GO TO CONVERT U4A00550 001D 610B 56 | BD010 LDX 1 11 INITIAL XR1 FOR OUTPUTING U4A00560 001E C82D 57 | LDD SAVAQ FETCH BIN U4A00570 001F D031 58 | STO HIHAF+1 SET UP HIGH ORDER HALF U4A00580 0020 1090 59 | SLT 16 AND U4A00590 0021 D02D 60 | STO LOHAF+1 LOW ORDER HALF FOR CONVERT U4A00600 61 | * U4A00610 62 | * U4A00620 0022 C82D 63 | BD020 LDD HIHAF U4A00630 0023 A81F 64 | D TEN DIVIDE OUT TENS U4A00640 0024 D02C 65 | STO HIHAF+1 RE-STORE RESULT U4A00650 66 | * U4A00660 0025 1090 67 | SLT 16 ADD REMAINDER U4A00670 0026 8827 68 | AD LOHAF TO LOW ORDER HALF U4A00680 0027 A81B 69 | D TEN AND DIVIDE OUT TENS. U4A00690 0028 D026 70 | STO LOHAF+1 RE-STORE RESULT U4A00700 71 | * U4A00710 0029 18D0 72 | RTE 16 SET TO SHIFT U4A00720 002A E81D 73 | OR SHIFT BY VALUE OF PREVIOUSLY U4A00730 002B D001 74 | STO BD030 SET UP SHIFT INSTRUCTION. U4A00740 75 | * U4A00750 002C C019 76 | LD H2000 HOLL ZERO (TWO BIT ON) U4A00760 002D 1800 77 | BD030 SRA *-* SHIFT INTO POSITION U4A00770 002E D500 0000 78 | BD040 STO L1 *-* ST INTO OUTPUT BUFFER U4A00780 0030 71FF 79 | MDX 1 -1 DECR XR1 U4A00790 0031 70F0 80 | MDX BD020 GO TO CONVERT NEXT CHAR U4A00800 81 | * U4A00810 0032 C014 82 | LD SIGN U4A00820 0033 7401 002FR 83 | MDX L BD040+1,+1 INCR OUTPUT ADDR U4A00830 0035 D480 002FR 84 | STO I BD040+1 SET SIGN INTO BUFFER U4A00840 0037 6500 0000 85 | SAV1 LDX L1 *-* RESTORE XR1 U4A00850 0039 6600 0000 86 | SAV2 LDX L2 *-* RESTORE XR2 U4A00860 003B 2000 87 | SAVST LDS 0 RESTORE STATUS U4A00870 003C C80F 88 | LDD SAVAQ STORE INTO OUTPUT BUFFER U4A00880 003D 4C00 0000 89 | BD060 BSC L *-* RETURN TO CALLER U4A00890 90 | * U4A00900 003F C004 91 | BD050 LD H80A0 SET SIGN U4A00910 0040 D006 92 | STO SIGN TO POSITIVE. U4A00920 0041 70DB 93 | MDX BD010 GO TO CONVERT BINARY U4A00930 94 | * U4A00940 0042 0001 95 | ONE DC 1 CONSTANT ONE U4A00950 0043 000A 96 | TEN DC 10 CONSTANT TEN U4A00960 0044 80A0 97 | H80A0 DC /80A0 HOLL PLUS U4A00970 0045 4000 98 | H4000 DC /4000 HOLL MINUS U4A00980 0046 2000 99 | H2000 DC /2000 HOLL ZERO U4A00990 0047 0000 100 | SIGN DC 0 TEMP STG FOR SIGN U4A01000 0048 1800 101 | SHIFT SRA *-* MOVE BIT TO POSITION U4A01010 102 | * U4A01020 004A 0CCC CCCC 103 | DUMMY DEC 214748364.B31 2**30 -8 U4A01030 004C 0000 0000 104 | SAVAQ DEC 0 TEMP BINARY BUFFER U4A01040 004E 0000 0000 105 | LOHAF DEC 0 TEMP FOR LOW ORDER U4A01050 0050 0000 0000 106 | HIHAF DEC 0 TEMP FOR HIGH ORDER U4A01060 0052 107 | END U4A01070 There were no errors in this assembly === CROSS REFERENCES ========================================================== Name Val Defd Referenced BD010 001DR 56 49 55 93 BD020 0022R 63 80 BD030 002DR 77 74 BD040 002ER 78 36 83 84 BD050 003FR 91 39 BD060 003DR 89 32 BIDEC 0000R 25 DUMMY 004AR 103 54 H2000 0046R 99 76 H4000 0045R 98 41 H80A0 0044R 97 91 HIHAF 0050R 106 58 63 65 LOHAF 004ER 105 60 68 70 ONE 0042R 95 SAV1 0037R 85 25 SAV2 0039R 86 37 SAVAQ 004CR 104 27 38 46 48 57 88 SAVST 003BR 87 28 SHIFT 0048R 101 73 SIGN 0047R 100 42 82 92 TEN 0043R 96 64 69