cdc:nos2.source:opl.opl871:deck:scrsim.001
Deck SCRSIM Part 001
4 Modifications
Listing Sections
- Deck SCRSIM Start
- Deck SCRSIM Part 1 (Line 1880)
Source
Seq # *Modification Id* Act ----------------------------+ 01880 M00S01839.scrsim +++| MX0 -12 01881 M00S01840.scrsim +++| BX6 -X0*X6 01882 M00S01841.scrsim +++| LX6 48 LEFT JUSTIFY 01883 M00S01842.scrsim +++| SA5 A6+B1 01884 M00S01843.scrsim +++| MX0 -48 01885 M00S01844.scrsim +++| BX7 -X0*X5 SAVE LOWER FIFTH WORD 01886 M00S01845.scrsim +++| BX7 X6+X7 01887 M00S01846.scrsim +++| SA7 A5 SAVE FIFTH WORD 01888 M00S01847.scrsim +++| LX2 2 01889 M00S01848.scrsim +++| SB4 A7 SET LAST ADDRESS 01890 M00S01849.scrsim +++| SB3 B1+ 01891 M00S01850.scrsim +++| EQ DYW1 01892 M00S01851.scrsim +++| TITLE DISPLAY BUFFER LINE NUMBER TABLES. 01893 M00S01852.scrsim +++|* LEFT SCREEN LINE NUMBER TABLE. 01894 M00S01853.scrsim +++| 01895 M00S01854.scrsim +++| 01896 M00S01855.scrsim +++| BLNT BSS 0 01897 M00S01856.scrsim +++| LOC 0 01898 M00S01857.scrsim +++| BSS 6 01899 M00S01858.scrsim +++| LHDR BSS 1 LEFT SCREEN HEADER 01900 M00S01859.scrsim +++| BSS 1 01901 M00S01860.scrsim +++| C16H BSS 1 HOLDING REGISTER HEADER 01902 M00S01861.scrsim +++| BSS 3 01903 M00S01862.scrsim +++| UB00 BSS 1 BYTE 0 HEADER 01904 M00S01863.scrsim +++| U04L BSS 1 BYTES 0-4 BINARY 01905 M00S01864.scrsim +++| OC00 BSS 1 BYTES 0-4 OCTAL 01906 M00S01865.scrsim +++| BSS 2 01907 M00S01866.scrsim +++| UB05 BSS 1 BYTE 5 HEADER 01908 M00S01867.scrsim +++| U09L BSS 1 BYTES 5-9 BINARY 01909 M00S01868.scrsim +++| OC05 BSS 1 BYTES 5-9 OCTAL 01910 M00S01869.scrsim +++| BSS 2 01911 M00S01870.scrsim +++| UB10 BSS 1 BYTE 10 HEADER 01912 M00S01871.scrsim +++| U14L BSS 1 BYTES 10-14 BINARY 01913 M00S01872.scrsim +++| OC10 BSS 1 BYTES 10-14 OCTAL 01914 M00S01873.scrsim +++| BSS 2 01915 M00S01874.scrsim +++| UB15 BSS 1 BYTE 15 HEADER 01916 M00S01875.scrsim +++| U16L BSS 1 BYTES 15-16 BINARY 01917 M00S01876.scrsim +++| OC15 BSS 1 BYTES 15-16 OCTAL 01918 M00S01877.scrsim +++| BSS 2 01919 M00S01878.scrsim +++| CNAL BSS 1 CHANNEL 36 NOT AVAILABLE MESSAGE LINE 01920 M00S01879.scrsim +++| BSS 1 01921 M00S01880.scrsim +++| PARM BSS 1 INPUT COMMAND LINE 01922 M00S01881.scrsim +++| MSGE BSS 1 ERROR MESSAGE LINE 01923 M00S01882.scrsim +++| BSS 2 01924 M00S01883.scrsim +++| ACTH BSS 1 S/C REGISTER HEADER 01925 M00S01884.scrsim +++| BSS 1 01926 M00S01885.scrsim +++| AC16 BSS 1 CHANNEL NUMBER LINE 01927 M00S01886.scrsim +++| W113 BSS 1 BYTES 4 - 0 S/C REGISTER 01928 M00S01887.scrsim +++| W114 BSS 1 BYTES 9 - 5 S/C REGISTER 01929 M00S01888.scrsim +++| W115 BSS 1 BYTES 14 - 10 S/C REGISTER 01930 M00S01889.scrsim +++| W116 BSS 1 BYTES 16 - 15 S/C REGISTER 01931 M00S01890.scrsim +++| ELNT EQU * 01932 M00S01891.scrsim +++| ERRNG 48-ELNT IF TOO MANY DISPLAY LINES 01933 M00S01892.scrsim +++| LOC *O 01934 M00S01893.scrsim +++| ORG BLNT 01935 M00S01894.scrsim +++| SPACE 4 01936 M00S01895.scrsim +++|* RIGHT SCREEN LINE NUMBER TABLE. 01937 M00S01896.scrsim +++| 01938 M00S01897.scrsim +++| 01939 M00S01898.scrsim +++| BRNT BSS 0 01940 M00S01899.scrsim +++| LOC 0 01941 M00S01900.scrsim +++| BSS 6 01942 M00S01901.scrsim +++| RHDR BSS 1 RIGHT SCREEN HEADER 01943 M00S01902.scrsim +++| BSS 1 01944 M00S01903.scrsim +++| PHDL BSS 1 COMMAND DESCRIPTION HEADER LINE 01945 M00S01904.scrsim +++| BSS 1 01946 M00S01905.scrsim +++| AREL BSS 1 AREA COMMAND 01947 M00S01906.scrsim +++| BSS 1 01948 M00S01907.scrsim +++| BYTL BSS 1 BYTE COMMAND 01949 M00S01908.scrsim +++| BSS 1 01950 M00S01909.scrsim +++| CLRL BSS 1 CLEAR COMMAND 01951 M00S01910.scrsim +++| BSS 1 01952 M00S01911.scrsim +++| CYCL BSS 1 CYCLE COMMAND 01953 M00S01912.scrsim +++| BSS 1 01954 M00S01913.scrsim +++| ENDL BSS 1 END COMMAND 01955 M00S01914.scrsim +++| BSS 1 01956 M00S01915.scrsim +++| LINL BSS 1 LINE COMMAND 01957 M00S01916.scrsim +++| BSS 1 01958 M00S01917.scrsim +++| REAL BSS 1 READ COMMAND 01959 M00S01918.scrsim +++| BSS 1 01960 M00S01919.scrsim +++| SETL BSS 1 SET COMMAND 01961 M00S01920.scrsim +++| BSS 3 01962 M00S01921.scrsim +++| PLUL BSS 1 + COMMAND 01963 M00S01922.scrsim +++| BSS 3 01964 M00S01923.scrsim +++| GOLL BSS 1 GO COMMAND 01965 M00S01924.scrsim +++| BSS 1 01966 M00S01925.scrsim +++| STOL BSS 1 STOP COMMAND 01967 M00S01926.scrsim +++| BSS 5 01968 M00S01927.scrsim +++| DECL BSS 1 DECIMAL BASE ASSUMED ON ARGUMENTS 01969 M00S01928.scrsim +++| SECL BSS 1 EXCLUDING OCTAL VALUES 01970 M00S01929.scrsim +++| VALL BSS 1 OCTAL VALUES LINE 01971 M00S01930.scrsim +++| ERNT EQU * 01972 M00S01931.scrsim +++| ERRNG 48-ERNT IF TOO MANY DISPLAY LINES 01973 M00S01932.scrsim +++| LOC *O 01974 M00S01933.scrsim +++| ORG BRNT 01975 M00S01934.scrsim +++| TITLE DISPLAY BUFFER. 01976 M00S01935.scrsim +++|* *K* DISPLAY LEFT SCREEN. 01977 M00S01936.scrsim +++| 01978 M00S01937.scrsim +++| 01979 M00S01938.scrsim +++| L. EQU * 01980 M00S01939.scrsim +++| L16 VFD 12/0,36/0,12/2 DISPLAY CONTROL WORD 01981 M00S01940.scrsim +++| 01982 M00S01941.scrsim +++| DSL 15,LHDR,(TEMPORARY HOLDING REGISTER CONTENTS) 01983 M00S01942.scrsim +++| DSL 15,LHDR,(TEMPORARY HOLDING REGISTER CONTENTS) 01984 M00S01943.scrsim +++| DSL 8,C16H,(CHANNEL 16 REGISTER - LINES 0-3) 01985 M00S01944.scrsim +++| DSL 8,C16H,(CHANNEL 16 REGISTER - LINES 0-3) 01986 M00S01945.scrsim +++| 01987 M00S01946.scrsim +++|* BINARY DISPLAY OF CHANNEL 16 HOLDING REGISTER CONTENTS. 01988 M00S01947.scrsim +++| 01989 M00S01948.scrsim +++| DSL 0,UB00,(BITS 59- 0) 01990 M00S01949.scrsim +++| DSL 55,UB00,(BYTE 00) 01991 M00S01950.scrsim +++| UL00 EQU * 01992 M00S01951.scrsim +++| DSL 0,U04L,(000000000000 000000000000 000000000000 ) 01993 M00S01952.scrsim +++| DSL 39,U04L,(000000000000 000000000000) 01994 M00S01953.scrsim +++| DSL 0,UB05,(BITS 119- 60) 01995 M00S01954.scrsim +++| DSL 55,UB05,(BYTE 05) 01996 M00S01955.scrsim +++| DSL 0,U09L,(000000000000 000000000000 000000000000 ) 01997 M00S01956.scrsim +++| DSL 39,U09L,(000000000000 000000000000) 01998 M00S01957.scrsim +++| DSL 0,UB10,(BITS 179-120) 01999 M00S01958.scrsim +++| DSL 55,UB10,(BYTE 10) 02000 M00S01959.scrsim +++| DSL 0,U14L,(000000000000 000000000000 000000000000 ) 02001 M00S01960.scrsim +++| DSL 39,U14L,(000000000000 000000000000) 02002 M00S01961.scrsim +++| DSL 0,UB15,(BITS 203-180) 02003 M00S01962.scrsim +++| DSL 55,UB15,(BYTE 15) 02004 M00S01963.scrsim +++| DSL 0,U16L,( ) 02005 M00S01964.scrsim +++| DSL 39,U16L,(000000000000 000000000000) 02006 M00S01965.scrsim +++| 02007 M00S01966.scrsim +++|* OCTAL DISPLAY OF CHANNEL 16 HOLDING REGISTER CONTENTS. 02008 M00S01967.scrsim +++| 02009 M00S01968.scrsim +++| UOC0 EQU * 02010 M00S01969.scrsim +++| DSL 2,OC00,( 0000) 02011 M00S01970.scrsim +++| DSL 15,OC00,( 0000) 02012 M00S01971.scrsim +++| DSL 28,OC00,( 0000) 02013 M00S01972.scrsim +++| DSL 41,OC00,( 0000) 02014 M00S01973.scrsim +++| DSL 54,OC00,( 0000) 02015 M00S01974.scrsim +++| DSL 2,OC05,( 0000) 02016 M00S01975.scrsim +++| DSL 15,OC05,( 0000) 02017 M00S01976.scrsim +++| DSL 28,OC05,( 0000) 02018 M00S01977.scrsim +++| DSL 41,OC05,( 0000) 02019 M00S01978.scrsim +++| DSL 54,OC05,( 0000) 02020 M00S01979.scrsim +++| DSL 2,OC10,( 0000) 02021 M00S01980.scrsim +++| DSL 15,OC10,( 0000) 02022 M00S01981.scrsim +++| DSL 28,OC10,( 0000) 02023 M00S01982.scrsim +++| DSL 41,OC10,( 0000) 02024 M00S01983.scrsim +++| DSL 54,OC10,( 0000) 02025 M00S01984.scrsim +++| DSL 2,OC15,( ) 02026 M00S01985.scrsim +++| DSL 15,OC15,( ) 02027 M00S01986.scrsim +++| DSL 28,OC15,( ) 02028 M00S01987.scrsim +++| DSL 41,OC15,( 0000) 02029 M00S01988.scrsim +++| DSL 54,OC15,( 0000) 02030 M00S01989.scrsim +++| 02031 M00S01990.scrsim +++|* CHANNEL 36 NOT AVAILABLE MESSAGE AREA. 02032 M00S01991.scrsim +++| 02033 M00S01992.scrsim +++| CNAW EQU *+1 02034 M00S01993.scrsim +++| DSL 15,CNAL,( ) 02035 M00S01994.scrsim +++| 02036 M00S01995.scrsim +++|* INPUT COMMAND AND ERROR MESSAGE AREA. 02037 M00S01996.scrsim +++| 02038 M00S01997.scrsim +++| PARL EQU *+1 02039 M00S01998.scrsim +++| DSL 2,PARM,( ) 02040 M00S01999.scrsim +++| DSL 48,PARM,( ) 02041 M00S02000.scrsim +++| MSGL EQU *+1 02042 M00S02001.scrsim +++| DSL 10,MSGE,( ) 02043 M00S02002.scrsim +++| DSL 18,ACTH,(ACTUAL S/C REGISTER CONTENTS) 02044 M00S02003.scrsim +++| DSL 22,AC16,(CHANNEL 16 REGISTER) 02045 M00S02004.scrsim +++| 02046 M00S02005.scrsim +++|* BINARY DISPLAY OF CHANNEL 16 S/C REGISTER CONTENTS. 02047 M00S02006.scrsim +++| 02048 M00S02007.scrsim +++| CH16 EQU * 02049 M00S02008.scrsim +++| DSL 0,W113,(000000000000 000000000000 000000000000 ) 02050 M00S02009.scrsim +++| DSL 39,W113,(000000000000 000000000000) 02051 M00S02010.scrsim +++| DSL 0,W114,(000000000000 000000000000 000000000000 ) 02052 M00S02011.scrsim +++| DSL 39,W114,(000000000000 000000000000) 02053 M00S02012.scrsim +++| DSL 0,W115,(000000000000 000000000000 000000000000 ) 02054 M00S02013.scrsim +++| DSL 39,W115,(000000000000 000000000000) 02055 M00S02014.scrsim +++| DSL 0,W116,( ) 02056 M00S02015.scrsim +++| DSL 39,W116,(000000000000 000000000000) 02057 M00S02016.scrsim +++| BSSZ 1 02058 M00S02017.scrsim +++| SPACE 4 02059 M00S02018.scrsim +++| M. EQU * 02060 M00S02019.scrsim +++| L36 VFD 12/0,36/0,12/2 DISPLAY CONTROL WORD 02061 M00S02020.scrsim +++| 02062 M00S02021.scrsim +++| DSL 15,LHDR,(TEMPORARY HOLDING REGISTER CONTENTS) 02063 M00S02022.scrsim +++| DSL 15,LHDR,(TEMPORARY HOLDING REGISTER CONTENTS) 02064 M00S02023.scrsim +++| DSL 8,C16H,(CHANNEL 36 REGISTER - LINES 0-3) 02065 M00S02024.scrsim +++| DSL 8,C16H,(CHANNEL 36 REGISTER - LINES 0-3) 02066 M00S02025.scrsim +++| 02067 M00S02026.scrsim +++|* BINARY DISPLAY OF CHANNEL 36 HOLDING REGISTER CONTENTS. 02068 M00S02027.scrsim +++| 02069 M00S02028.scrsim +++| DSL 0,UB00,(BITS 59- 0) 02070 M00S02029.scrsim +++| DSL 55,UB00,(BYTE 00) 02071 M00S02030.scrsim +++| LL00 EQU * 02072 M00S02031.scrsim +++| DSL 0,U04L,(000000000000 000000000000 000000000000 ) 02073 M00S02032.scrsim +++| DSL 39,U04L,(000000000000 000000000000) 02074 M00S02033.scrsim +++| DSL 0,UB05,(BITS 119- 60) 02075 M00S02034.scrsim +++| DSL 55,UB05,(BYTE 05) 02076 M00S02035.scrsim +++| DSL 0,U09L,(000000000000 000000000000 000000000000 ) 02077 M00S02036.scrsim +++| DSL 39,U09L,(000000000000 000000000000) 02078 M00S02037.scrsim +++| DSL 0,UB10,(BITS 179-120) 02079 M00S02038.scrsim +++| DSL 55,UB10,(BYTE 10) 02080 M00S02039.scrsim +++| DSL 0,U14L,(000000000000 000000000000 000000000000 ) 02081 M00S02040.scrsim +++| DSL 39,U14L,(000000000000 000000000000) 02082 M00S02041.scrsim +++| DSL 0,UB15,(BITS 203-180) 02083 M00S02042.scrsim +++| DSL 55,UB15,(BYTE 15) 02084 M00S02043.scrsim +++| DSL 0,U16L,( ) 02085 M00S02044.scrsim +++| DSL 39,U16L,(000000000000 000000000000) 02086 M00S02045.scrsim +++| 02087 M00S02046.scrsim +++|* OCTAL DISPLAY OF CHANNEL 36 HOLDING REGISTER CONTENTS. 02088 M00S02047.scrsim +++| 02089 M00S02048.scrsim +++| LOC0 EQU * 02090 M00S02049.scrsim +++| DSL 2,OC00,( 0000) 02091 M00S02050.scrsim +++| DSL 15,OC00,( 0000) 02092 M00S02051.scrsim +++| DSL 28,OC00,( 0000) 02093 M00S02052.scrsim +++| DSL 41,OC00,( 0000) 02094 M00S02053.scrsim +++| DSL 54,OC00,( 0000) 02095 M00S02054.scrsim +++| DSL 2,OC05,( 0000) 02096 M00S02055.scrsim +++| DSL 15,OC05,( 0000) 02097 M00S02056.scrsim +++| DSL 28,OC05,( 0000) 02098 M00S02057.scrsim +++| DSL 41,OC05,( 0000) 02099 M00S02058.scrsim +++| DSL 54,OC05,( 0000) 02100 M00S02059.scrsim +++| DSL 2,OC10,( 0000) 02101 M00S02060.scrsim +++| DSL 15,OC10,( 0000) 02102 M00S02061.scrsim +++| DSL 28,OC10,( 0000) 02103 M00S02062.scrsim +++| DSL 41,OC10,( 0000) 02104 M00S02063.scrsim +++| DSL 54,OC10,( 0000) 02105 M00S02064.scrsim +++| DSL 2,OC15,( ) 02106 M00S02065.scrsim +++| DSL 15,OC15,( ) 02107 M00S02066.scrsim +++| DSL 28,OC15,( ) 02108 M00S02067.scrsim +++| DSL 41,OC15,( 0000) 02109 M00S02068.scrsim +++| DSL 54,OC15,( 0000) 02110 M00S02069.scrsim +++| 02111 M00S02070.scrsim +++|* INPUT COMMAND AND ERROR MESSAGE AREA. 02112 M00S02071.scrsim +++| 02113 M00S02072.scrsim +++| PARK EQU *+1 02114 M00S02073.scrsim +++| DSL 2,PARM,( ) 02115 M00S02074.scrsim +++| DSL 48,PARM,( ) 02116 M00S02075.scrsim +++| MSGK EQU *+1 02117 M00S02076.scrsim +++| DSL 10,MSGE,( ) 02118 M00S02077.scrsim +++| DSL 18,ACTH,(ACTUAL S/C REGISTER CONTENTS) 02119 M00S02078.scrsim +++| DSL 22,AC16,(CHANNEL 36 REGISTER) 02120 M00S02079.scrsim +++| 02121 M00S02080.scrsim +++|* BINARY DISPLAY OF CHANNEL 36 S/C REGISTER CONTENTS. 02122 M00S02081.scrsim +++| 02123 M00S02082.scrsim +++| CH36 EQU * 02124 M00S02083.scrsim +++| DSL 0,W113,(000000000000 000000000000 000000000000 ) 02125 M00S02084.scrsim +++| DSL 39,W113,(000000000000 000000000000) 02126 M00S02085.scrsim +++| DSL 0,W114,(000000000000 000000000000 000000000000 ) 02127 M00S02086.scrsim +++| DSL 39,W114,(000000000000 000000000000) 02128 M00S02087.scrsim +++| DSL 0,W115,(000000000000 000000000000 000000000000 ) 02129 M00S02088.scrsim +++| DSL 39,W115,(000000000000 000000000000) 02130 M00S02089.scrsim +++| DSL 0,W116,( ) 02131 M00S02090.scrsim +++| DSL 39,W116,(000000000000 000000000000) 02132 M00S02091.scrsim +++| BSSZ 1 02133 M00S02092.scrsim +++| SPACE 4 02134 M00S02093.scrsim +++|* *K* DISPLAY RIGHT SCREEN. 02135 M00S02094.scrsim +++| 02136 M00S02095.scrsim +++| 02137 M00S02096.scrsim +++| R. EQU * 02138 M00S02097.scrsim +++| R VFD 12/0,36/0,12/2 DISPLAY CONTROL WORD 02139 M00S02098.scrsim +++| 02140 M00S02099.scrsim +++| DSL 23,RHDR,(SIMULATOR COMMANDS) 02141 M00S02100.scrsim +++| DSL 8,PHDL,(COMMAND) 02142 M00S02101.scrsim +++| DSL 34,PHDL,(DESCRIPTION) 02143 M00S02102.scrsim +++| DSL 0,AREL,(AREA,A,M,Y.) 02144 M00S02103.scrsim +++| DSL 24,AREL,(SET M BITS FROM A TO OCTAL VALUE Y) 02145 M00S02104.scrsim +++| DSL 0,BYTL,(BYTE,XX,YYYY.) 02146 M00S02105.scrsim +++| DSL 24,BYTL,(SET BYTE XX TO OCTAL VALUE YYYY) 02147 M00S02106.scrsim +++| DSL 0,CLRL,(CLEAR,A,B,...,Z.) 02148 M00S02107.scrsim +++| DSL 24,CLRL,(CLEAR BITS A,B,...,Z) 02149 M00S02108.scrsim +++| DSL 0,CYCL,(CYCLE,X,T,R.) 02150 M00S02109.scrsim +++| DSL 24,CYCL,(SET BIT X EVERY 16*T MS. R TIMES) 02151 M00S02110.scrsim +++| DSL 0,ENDL,(END.) 02152 M00S02111.scrsim +++| DSL 24,ENDL,(END CYCLE COMMAND BEFORE R REACHED) 02153 M00S02112.scrsim +++| DSL 0,LINL,(LINE,X,Y.) 02154 M00S02113.scrsim +++| DSL 24,LINL,(SET LINE X TO OCTAL VALUE Y) 02155 M00S02114.scrsim +++| DSL 0,REAL,(READ.) 02156 M00S02115.scrsim +++| DSL 24,REAL,(READ S/C REGISTER INTO HOLDING REGISTER) 02157 M00S02116.scrsim +++| DSL 0,SETL,(SET,A,B,...,Z.) 02158 M00S02117.scrsim +++| DSL 24,SETL,(SET BITS A,B,...,Z) 02159 M00S02118.scrsim +++| DSL 0,PLUL,(+.) 02160 M00S02119.scrsim +++| DSL 24,PLUL,(CHANGE REGISTER BEING USED AND K DISPLAY) 02161 M00S02120.scrsim +++| DSL 0,GOLL,(GO.) 02162 M00S02121.scrsim +++| DSL 24,GOLL,(ENTER HOLDING REGISTERS IN S/C REGISTERS) 02163 M00S02122.scrsim +++| DSL 0,STOL,(STOP.) 02164 M00S02123.scrsim +++| DSL 24,STOL,(END THE SIMULATOR) 02165 M00S02124.scrsim +++| DSL 0,DECL,(ALL BIT, BYTE, AND LINE NUMBERS ASSUMED ) 02166 M00S02125.scrsim +++| DSL 40,DECL,(DECIMAL.) 02167 M00S02126.scrsim +++| DSL 0,SECL,(TIME VALUES ASSUMED DECIMAL) 02168 M00S02127.scrsim +++| DSL 0,VALL,(Y AND YYYY VALUES MUST BE OCTAL.) 02169 M00S02128.scrsim +++| BSSZ 1 02170 M00S02129.scrsim +++| SPACE 4 02171 M00S02130.scrsim +++|* COMMON DECKS. 02172 M00S02131.scrsim +++| 02173 M00S02132.scrsim +++|*CALL COMCCIO 02174 M00S02133.scrsim +++|*CALL COMCCOD 02175 M00S02134.scrsim +++|*CALL COMCCPM 02176 M00S02135.scrsim +++|*CALL COMCDXB 02177 M00S02136.scrsim +++|*CALL COMCMVE 02178 M00S02137.scrsim +++|*CALL COMCRDC 02179 M00S02138.scrsim +++|*CALL COMCRDW 02180 M00S02139.scrsim +++|*CALL COMCSYS 02181 M00S02140.scrsim +++| 02182 M00S02141.scrsim +++| 02183 M00S02142.scrsim +++| USE LITERALS 02184 M00S02143.scrsim +++| SPACE 4 02185 M00S02144.scrsim +++|* BUFFERS. 02186 M00S02145.scrsim +++| 02187 M00S02146.scrsim +++| 02188 M00S02147.scrsim +++| IBUF EQU * FET INPUT BUFFER 02189 M00S02148.scrsim +++| OBUF EQU IBUF+IBUFL OUTPUT BUFFER 02190 M00S02149.scrsim +++| RFL= EQU OBUF+OBUFL+100B 02191 M00S02150.scrsim +++| PRS TITLE PRESET. 02192 M00S02151.scrsim +++|** PRS - PRESET. 02193 M00S02152.scrsim +++|* 02194 M00S02153.scrsim +++|* EXIT (CA) = 1 IF CHANNEL 36 NOT AVAILABLE. 02195 M00S02154.scrsim +++|* *K* DISPLAY INITIALIZED. 02196 M00S02155.scrsim +++|* 02197 M00S02156.scrsim +++|* USES X - 0, 1, 2, 6, 7. 02198 M00S02157.scrsim +++|* A - 1, 2, 6. 02199 M00S02158.scrsim +++| 02200 M00S02159.scrsim +++| 02201 M00S02160.scrsim +++| PRS SUBR ENTRY/EXIT 02202 M00S02161.scrsim +++| 02203 M00S02162.scrsim +++|* CHECK CYBER 170 BIT AND NUMBER OF PP-S. 02204 M00S02163.scrsim +++|
| Line S02164 Modification History | |
|---|---|
M01 (Removed by) | ns21000 |
Seq # *Modification Id* Act ----------------------------+ 02205 M01S02164.ns21000 ---| SYSTEM RSB,R,PRSC 02206 M01S02165.ns21000 ---| SA1 PRSB WORD PPUL OF CMR 02207 M01S02166.ns21000 ---| LX1 59-16 02208 M01S02167.ns21000 ---| PL X1,PRS1 IF NOT CYBER 170 02209 M01S02168.ns21000 ---| AX1 7
| Line S00005 Modification History | |
|---|---|
M01 (Added by) | ns21000 |
Seq # *Modification Id* Act ----------------------------+ 02210 M01S00005.ns21000 +++| SYSTEM RSB,R,PRSE 02211 M01S00006.ns21000 +++| SA1 PRSD CMR WORD *MABL* 02212 M01S00007.ns21000 +++| LX1 59-43 02213 M01S00008.ns21000 +++| LX2 X1,B1 02214 M01S00009.ns21000 +++| PL X1,PRS0 IF CYBER 70 INTERLOCK REGISTER 02215 M01S00010.ns21000 +++| NG X2,PRS3 IF NOT CYBER 170 STATUS CONTROL REGISTER 02216 M01S00011.ns21000 +++| PRS0 SYSTEM RSB,R,PRSC 02217 M01S00012.ns21000 +++| SA1 PRSB CMR WORD *PPUL* 02218 M01S00013.ns21000 +++| AX1 24 02219 M00S02169.scrsim +++| MX0 -12 02220 M00S02170.scrsim +++| BX1 -X0*X1 NUMBER OF PP-S 02221 M00S02171.scrsim +++| SX6 11 02222 M00S02172.scrsim +++| IX6 X1-X6 02223 M00S02173.scrsim +++| PL X6,PRS2 IF CHANNEL 36 AVAILABLE 02224 M00S02174.scrsim +++| PRS1 SX6 B1+ SET CHANNEL 36 NOT AVAILABLE 02225 M00S02175.scrsim +++| SA6 CA 02226 M00S02176.scrsim +++| MOVE 3,PRSA,CNAW *CHANNEL 36 NOT AVAILABLE* 02227 M00S02177.scrsim +++| 02228 M00S02178.scrsim +++|* INITIALIZE *K* DISPLAY. 02229 M00S02179.scrsim +++| 02230 M00S02180.scrsim +++| PRS2 CONSOLE K INITIALIZE *K* DISPLAY 02231 M00S02181.scrsim +++| EQ PRSX RETURN
| Line S00014 Modification History | |
|---|---|
M01 (Added by) | ns21000 |
Seq # *Modification Id* Act ----------------------------+ 02232 M01S00014.ns21000 +++| 02233 M01S00015.ns21000 +++| PRS3 MESSAGE PRSF,0,R * NO SCR ON MAINFRAME.* 02234 M01S00016.ns21000 +++| ABORT TERMINATE PROGRAM 02235 M01S00017.ns21000 +++| 02236 M00S02182.scrsim +++| 02237 M00S02183.scrsim +++| PRSA DIS 3,CHANNEL 36 NOT AVAILABLE 02238 M00S02184.scrsim +++| BSSZ 1 02239 M00S02185.scrsim +++| PRSB VFD 1/1,59/0 02240 M00S02186.scrsim +++| PRSC VFD 24/1,18/PPUL,18/PRSB RSB CONTROL WORD
| Line S00018 Modification History | |
|---|---|
M01 (Added by) | ns21000 |
Seq # *Modification Id* Act ----------------------------+ 02241 M01S00018.ns21000 +++| PRSD VFD 1/1,59/0 02242 M01S00019.ns21000 +++| PRSE VFD 24/1,18/MABL,18/PRSD RSB CONTROL WORD 02243 M01S00020.ns21000 +++| PRSF DATA C* NO SCR ON MAINFRAME.* 02244 M00S02187.scrsim +++| SPACE 4 02245 M00S02188.scrsim +++| END
cdc/nos2.source/opl.opl871/deck/scrsim.001.txt · Last modified: by 127.0.0.1