ibm:ibm1130-lib:dmsr2v12:s3xdd_lst
S3XDD
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- s3xdd.lst
ASM1130 CROSS ASSEMBLER V1.22 -- V2M12 -- Sun Nov 1 19:25:08 2020 Source File: \s3xdd.asm 1 | *************************************************** S3G00010 2 | * * S3G00020 3 | * SUBROUTINE NAME- * S3G00030 4 | * FULL NAME- FIXED-POINT (FRACTIONAL) DOUBLE-* S3G00040 5 | * WORD DIVIDE FUNCTION. * S3G00050 6 | * CODE NAME- XDD * S3G00060 7 | * PURPOSE- THIS FUNCTION PERFORMS A FIXED-POINT * S3G00070 8 | * DIVIDE ON TWO FIXED-POINT DOUBLE-WORD * S3G00080 9 | * FRACTIONS. * S3G00090 10 | * METHOD-SEE IBM 1130 SUBROUTINE LIBRARY MANUAL.* S3G00100 11 | * CAPABILITIES AND LIMITATIONS- SEE IBM 1130 * S3G00110 12 | * SUBROUTINE LIBRARY MANUAL. * S3G00120 13 | * SPECIAL FEATURES- N/A * S3G00130 14 | * ADDITIONAL INFORMATION- * S3G00140 15 | * ESTIMATED EXECUTION TIME- SEE IBM 1130 * S3G00150 16 | * SUBROUTINE LIBRARY MANUAL * S3G00160 17 | * OTHER- A PERIOD FOLLOWED BY B, APPEARING TO* S3G00170 18 | * THE RIGHT OF COMMENT, INDICATES THAT THE* S3G00180 19 | * NUMBER FOLLOWING IS THE BINARY POINT OF * S3G00190 20 | * THE NUMBER PRESENTLY IN THE ACCUMULATOR.* S3G00200 21 | * LET C REFER TO THE TRUE EXPONENT OF THE * S3G00210 22 | * INPUT ARGUMENT. * S3G00220 23 | * * S3G00230 24 | *************************************************** S3G00240 LIBF XDD -V1. 26 | LIBR S3G00260 27 | ENT XDD S3G00270 0000 7002 28 | XDD MDX *+2 S3G00280 0001 4C80 0000 29 | XDDX BSC I *-* LOADER INSERT. S3G00290 0003 2829 30 | STS XDSS SAVE STATUS S3G00300 0004 D83D 31 | STD DVR STORE DIVISOR S3G00310 0005 4810 32 | BSC - IF PTV, EXT NON-ZERO CAUSES S3G00320 0006 883F 33 | AD B16 CARRY INTO ACC. SAVE ONE S3G00330 0007 D033 34 | STO DVR1 WD APPROXIMATE DIVISOR. S3G00340 0008 CB7E 35 | LDD 3 126 STORE DIVIDEND. S3G00350 0009 D83A 36 | STD DIVND S3G00360 000A 10A0 37 | SLT 32 S3G00370 000B DB7E 38 | STD 3 126 CLEAR INITIAL QUOTIENT. S3G00380 000C C030 39 | LD DIVNP RESET TO NORMAL PROCESS. S3G00390 000D D016 40 | STO DIV2 S3G00400 000E 4C01 0031R 41 | BSC L DIVOP,O OVFL MEANS DVR1=+1.0 S3G00410 42 | * SO BRANCH TO SIMULATE S3G00420 43 | * DIVISION BY ONE. S3G00430 0010 C833 44 | LDD DIVND GET DIVIDEND S3G00440 0011 4828 45 | BSC +Z SKIP IF NOT NEG S3G00450 0012 882D 46 | AD ONED IF NEG,SCALE BY ONE S3G00460 0013 1881 47 | SRT 1 SHIFT FOR DIVISION. S3G00470 48 | * S3G00480 49 | *COMPUTE PARTIAL QUOTIENTS S3G00490 50 | * S3G00500 0014 A826 51 | D DVR1 PERFORM FIRST DIVISION S3G00510 0015 D37E 52 | STO 3 126 SAVE Q1=DVD/DVR1 .B0 S3G00520 0016 10A0 53 | SLT 32 CLEAR ACC AND EXT S3G00530 0017 982A 54 | SD DVR COMPUTE AN ERROR TO GET S3G00540 0018 2750*4000 55 | LIBF XMD Q2. ERROR1=DVD-Q1*DVR .B0 S3G00550 0019 882A 56 | AD DIVND .B0 S3G00560 001A 108C 57 | SLT 12 SCALE ERROR1 FOR .B-12 S3G00570 001B A81F 58 | D DVR1 DIVISION BY DVR1 .B-13 S3G00580 001C 1890 59 | SRT 16 MOVE RESULTANT CORRECTION S3G00590 001D 1083 60 | SLT 3 FOR FIRST QUOTIENT TO S3G00600 001E 8B7E 61 | DIV16 AD 3 126 PROPER POSITION,TRUNCATING. S3G00610 001F DB7E 62 | STD 3 126 ST Q2=Q1+ERROR1/DVR1 S3G00620 0020 10A0 63 | SLT 32 CLEAR ACC AND EXT TO S3G00630 0021 9820 64 | SD DVR GET NEXT PARTIAL QUOTIENT S3G00640 0022 2750*4000 65 | LIBF XMD COMPUTE -Q2*DVR S3G00650 0023 8820 66 | AD DIVND ERROR2=DVD-Q2*DVR .B0 S3G00660 0024 7000 67 | DIV2 MDX X *-* NOP OR BR TO DIV15 S3G00670 0025 1092 68 | DIV1 SLT 18 SCALE TO PERFORM .B-18 S3G00680 0026 A814 69 | D DVR1 DIVISION BY DVR1 .B-19 S3G00690 0027 4828 70 | BSC +Z IF NEG ROUND OFF QUOTIENT S3G00700 0028 801F 71 | A DIV7 TO 4TH BIT S3G00710 0029 1893 72 | SRT 19 POSITION PARTIAL QUOTIENT S3G00720 002A 8B7E 73 | DIVX AD 3 126 AND ADD TO PREVIOUS CALC.B0 S3G00730 74 | * S3G00740 75 | *SET OVERFLOW INDR FOR RETURN S3G00750 76 | * S3G00760 002B 4C01 002FR 77 | BSC L *+2,O IF OVERFLO ON WHEN ENTERED S3G00770 002D 2000 78 | XDSS LDS *-* OR TURNED ON BY IMPROPER S3G00780 002E 70D2 79 | MDX XDDX DIVIDE,TURN ON OVERFLOW S3G00790 002F 2003 80 | LDS 3 INDR. RET TO MAIN PROG S3G00800 0030 70D0 81 | MDX XDDX S3G00810 82 | * S3G00820 83 | *SECTION TO SIMULATE DIVISION BY ONE IF THE INITIAL S3G00830 84 | *APPROXIMATE DIVISOR IS ONE. S3G00840 85 | * S3G00850 0031 C00D 86 | DIVOP LD DIVXP BRANCH TO DIV15 AT DIV2 S3G00860 0032 D0F1 87 | STO DIV2 TO SIMULATE DIV BY +1.0 S3G00870 0033 C00A 88 | LD THREE ITERATION COUNT. S3G00880 0034 D007 89 | STO DIVCT S3G00890 0035 C80E 90 | LDD DIVND INITIAL QUOTIENT IS S3G00900 0036 70E7 91 | MDX DIV16 DIVIDEND ITSELF. S3G00910 0037 74FF 003CR 92 | DIV15 MDX L DIVCT,-1 DECR DIVIDE CTR S3G00920 0039 70E4 93 | MDX DIV16 IF NOT ZERO,RET TO DIVIDE S3G00930 003A 70EF 94 | MDX DIVX IF ZERO,GO PREPARE EXIT S3G00940 95 | * S3G00950 96 | *CONSTANTS AND BUFFER AREA S3G00960 97 | * S3G00970 003B 0000 98 | DVR1 DC 0 ONE-WD APPROXIMATE DIVISOR S3G00980 003C 0000 99 | DIVCT DC 0 DIVIDE ITERATION COUNT. S3G00990 003D 1000 100 | DIVNP NOP INST FOR NORMAL PROCESS S3G01000 003E 0003 101 | THREE DC 3 DIVIDE COUNT CON S3G01010 003F 7012 102 | DIVXP MDX X DIV15-DIV2-1 INST USED WHEN DVR1=1 S3G01020 0040 0000 0001 103 | ONED DEC 1 TWO WORD ONE S3G01030 0042 0000 0000 104 | DVR DEC 0 ROUND OFF CON S3G01040 0044 0000 0000 105 | DIVND DEC 0 DIVIDEND BUFFER S3G01050 0046 0000 FFFF 106 | B16 DEC 65535 (/FFFF) S3G01060 0048 0007 107 | DIV7 DC 7 S3G01070 0049 108 | END S3G01080 There were no errors in this assembly === CROSS REFERENCES ========================================================== Name Val Defd Referenced B16 0046R 106 33 DIV1 0025R 68 DIV15 0037R 92 102 DIV16 001ER 61 91 93 DIV2 0024R 67 40 87 102 DIV7 0048R 107 71 DIVCT 003CR 99 89 92 DIVND 0044R 105 36 44 56 66 90 DIVNP 003DR 100 39 DIVOP 0031R 86 41 DIVX 002AR 73 94 DIVXP 003FR 102 86 DVR 0042R 104 31 54 64 DVR1 003BR 98 34 51 58 69 ONED 0040R 103 46 THREE 003ER 101 88 XDD 0000R 28 XDDX 0001R 29 79 81 XDSS 002DR 78 30
ibm/ibm1130-lib/dmsr2v12/s3xdd_lst.txt · Last modified: 2023/08/06 13:34 by Site Administrator